1. Field of the Invention
The present invention relates to a semiconductor device having a configuration in which a signal readout from a memory cell and transmitted through a bit line is amplified by a sense amplifier.
2. Description of Related Art
Conventionally, a configuration of a semiconductor memory device such as a DRAM is known in which a sense amplifier sensing and amplifying a signal readout from a memory cell through a bit line and a read circuit transmitting an output signal of the sense amplifier to a final stage amplifier through hierarchical data lines (Refer to, for example, Japanese Patent Application Laid-open No. 2001-57080). In the above conventional read circuit, the output signal of the sense amplifier is transmitted sequentially from a local data line to a main data line and inputted to the final stage amplifier. Generally, an N-channel type transistor as a transfer gate is used to connect between the local data line and the main data line or between each data line and a node in the final stage amplifier. In this case, a configuration in which the N-channel type transistor is replaced with a P-channel type transistor can be employed, or a configuration in which both the N-channel type transistor and the P-channel type transistor are used can be employed. Or, a configuration is known in which a sub amplifier is provided halfway in the local/main data lines so as to secondarily amplify the transmission signal in order to prevent a decrease in reading speed due to an increase in parasitic capacitance.
For example, in an example case where a signal is transmitted sequentially through a pair of local data lines and a pair of main data lines corresponding to a complementary pair of bit lines, the output signal of the sense amplifier which is selected by a column select signal is sequentially transmitted as a voltage difference of each pair of the data lines. At this point, the pair of main data lines are previously precharged to a predetermined voltage and the voltage difference is generated by drawing charge from one of the pair of main data lines. Then, the voltage difference is transmitted to the final stage amplifier through the transfer gate, and data can be outputted to outside with a desired amplitude.
However, an external supply voltage or an internal supply voltage obtained by stepping down the external supply voltage is supplied to the above read circuit, and a gate voltage for turning on the N-channel type transistor as the transfer gate is controlled based on the supply voltage. Therefore, the voltage difference of the main data lines having a large parasitic capacitance is required to have a sufficiently large amplitude in order that an amplitude at the final stage amplifier becomes sufficiently large, and there has been an event that an operation current required in a precharge operation or the like increases. Particularly, influence of the increase in the operation current becomes large when the number of output bits is increased with the improvement of integration of the semiconductor memory device.
Further, when data is sensed by using a charge transfer transistor, it is required to suppress a decrease in transfer ability of the charge transfer transistor, which is caused by gate coupling with which a potential of its gate terminal is influenced by a voltage transition of source or drain terminal of the charge transfer transistor.